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Problem worth solving

In large chip designs, bursts of computing activity in one of the modules can cause local supply voltage droops that increase delays and result in timing violations. Such voltage droops can be accommodated by adding clock margins, but this results in a significant performance hit. In contrast, adaptive strategies detect such events and either temporarily stop the clock, or initiate a rollback to a previous state, or reduce the clock frequency to prevent timing violations.

The performance of such solutions critically depends on a very fast response to droops. State-of-the-art solutions either employ analog adjustment techniques, or digital schemes that are slow to respond. Analog circuit solutions work well, but are undesirable because they require special design, calibration, and are large, power consuming circuits. Digital solutions require sampling of an analog time-varying signal, the supply voltage, and thus can encounter metastability. Existing digital solutions employ specially designed synchronizer circuits that reduce, to almost zero, the probability of metastable event failures. However, the synchronization incurs multiple clock cycles of delay.

The Solution

Researchers have developed an all-digital circuit that can respond to voltage droops within a fraction of a clock cycle. This is achieved by using (potentially metastable) control signals to delay clock signals, while concurrently performing the control signal synchronization. This “metastability-containing” approach greatly improves the responsiveness to voltage droops, increasing performance or reducing energy consumption by at least 10%. They have extensively simulated the design and have developed an ASIC demonstrator circuit in collaboration with IHP Microelectronics, supported by an ERC Proof of Concept grant. This all-digital solution can be implemented using existing tools and flows, and is easily adaptable to new technology.

Use Cases

Chip designs where high frequency operation is critical: FastVolt can achieve faster response time to voltage droops, yielding at least 10% improvement.

Chips that have real-time operation demands: our scheme does not stop the clock.

Chips that operate at low voltage: timing is very sensitive to voltage variations.

FPGAs, which currently restrict operating frequency to deal with worst-case voltage droop


The technology is expected to serve the key players in the semiconductor chip industry. These who would incorporate the new chip design into their products for specific, niche or high-power applications.


FastVolt technology is being developed by a team of distinguished researchers in Distributed and Embedded Systems at the Department for Algorithms and Complexity at Max Plank Institut Informatik.